Biased Darlington transistor pair, method, and system

ABSTRACT

An amplifier includes a Darlington transistor pair and a biasing network to increase bias currents in an input transistor.

FIELD

The present invention relates generally to electronic circuits, and morespecifically to Darlington transistor pairs.

BACKGROUND

A “Darlington transistor pair” includes two transistors coupled in ahigh-gain fashion. The first transistor receives an input signal,amplifies it, and drives the second transistor which amplifies itfurther.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-3 show circuit diagrams including Darlington transistor pairs inaccordance with various embodiments of the present invention;

FIGS. 4 and 5 show block diagrams of electronic systems in accordancewith various embodiments of the present invention; and

FIG. 6 shows a flowchart in accordance with various embodiments of thepresent invention.

DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that the variousembodiments of the invention, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein in connection with one embodiment may beimplemented within other embodiments without departing from the spiritand scope of the invention. In addition, it is to be understood that thelocation or arrangement of individual elements within each disclosedembodiment may be modified without departing from the spirit and scopeof the invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the appended claims, appropriately interpreted, alongwith the full range of equivalents to which the claims are entitled. Inthe drawings, like numerals refer to the same or similar functionalitythroughout the several views.

FIG. 1 shows a circuit diagram including a Darlington transistor pair inaccordance with various embodiments of the present invention. Circuit100 includes input transistor 110, second transistor 120, radiofrequency (RF) choke 112, degeneration inductor 122, capacitor 132, andvoltage controlled current source 130. Input transistor 110 and secondtransistor 120 are coupled to form a Darlington transistor pair with thecollectors coupled together at node 142, and the emitter of inputtransistor 110 coupled to the base of transistor 120 at node 111.

As shown in FIG. 1, transistors 110 and 120 may be bipolar junctiontransistors (BJTs). In some embodiments, transistors 110 and 120 areheterojunction bipolar transistors (HBTs), such as those manufacturedusing an Indium Phosphide (InP) process, although this is not alimitation of the present invention. For example, one or both oftransistors 110 and 120 may be an isolated gate transistor (IGFET) suchas a metal oxide semiconductor field effect transistor (MOSFET).

Radio frequency choke 112 is coupled between upper power supply node 113and the collectors of transistors 110 and 120. In some embodiments, RFchoke 112 is an inductive collector load providing output impedancematching and a collector bias current without the voltage drop of aresistor. Biasing without a resistant voltage drop allows for high gainand high dynamic range in a particular bandwidth without saturatingtransistors 110 and 120.

Degeneration inductor 122 is coupled between the emitter of transistor120 and lower power supply node 114. In some embodiments, inductiveemitter degeneration helps to tune input impedance matching and mayimprove amplifier linearity. Further, in some embodiments, inductiveemitter degeneration sets the gain of the amplifier in the bandwidth ofinterest without adding the thermal noise associated with a resistor,and desensitizes the amplifier to Beta variation.

Capacitor 132 is coupled between signal input node 140 and the baseterminal of transistor 110. Capacitor 132 allows alternating current(AC) components of an input signal to pass from node 140 to the baseterminal of input transistor 110, and blocks direct current (DC)components of the input signal from passing from node 140 to the baseterminal of input transistor 110.

In operation, an input signal (VIN) is received on signal input node140, and AC components of the signal are transferred to the baseterminal of input transistor 110. Input transistor 110 amplifies theinput signal and provides it to second transistor 120. Second transistor120 further amplifies the signal, and provides an amplified outputsignal (VOUT) on signal output node 142.

The base terminal of input transistor 110 receives a bias voltage(VBIAS1), and the emitter of input transistor 110 receives a biasvoltage (V1) on node 111 from voltage controlled current source 130. Insome embodiments, V1 is substantially equal to Vbe, where Vbe is theminimum base-to-emitter voltage necessary to bias transistor 120 in theforward active region. Also in some embodiments, VBIAS1 is substantiallyequal to 2Vbe. In other embodiments, V1 is greater than Vbe, and VBIAS1is greater than 2Vbe.

Voltage controlled current source 130 is coupled between node 111 andlower power supply node 114. In some embodiments, voltage controlledcurrent source 130 provides the bias voltage V1 in response to areceived bias voltage (VBIAS2). In some embodiments, voltage controlledcurrent source 130 operates to keep V1 in a substantially constantrelationship to VBIAS2. For example, in some embodiments, voltagecontrolled current source 130 works to maintain V1 substantially equalto VBIAS2. Voltage controlled current source 130 provides a voltage pathto node 111, and also provides a current path from node 111 to lowerpower supply node 114.

The combination of the bias voltage on the base terminal of transistor110, the bias voltage on node 111, and the current path from node 111 tolower power supply node 114 allow for an increase in the base-to-emitterand collector-to-emitter bias currents of transistor 110. By increasingthe bias currents of input transistor 110, operating characteristics oftransistor 110 may be modified. For example, an increase in bias currentmay increase the gain-bandwidth product and the maximum operatingfrequency of transistor 110, and may also decrease noise. In someembodiments, the frequency of operation versus noise may also be tradedoff through adjustment of the various bias currents of input transistor110.

FIG. 2 shows a diagram of a circuit including a Darlington transistorpair in accordance with various embodiments of the present invention.Circuit 200 includes input transistor 110, second transistor 120, RFchoke 112, degeneration inductor 122, capacitor 132, amplifier 210, andlow pass filters 220, 230, and 240.

An output node of amplifier 210 is coupled to node 111 through low passfilter 230, and node 111 is fed back to an input of amplifier 210through low pass filter 240. Amplifier 210 also receives VBIAS2 on aninput node. In this configuration, amplifier 210 is coupled as an erroramplifier that operates to force V1 to be substantially equal to VBIAS2.

In some embodiments, amplifier 210 is an operational amplifier, and inother embodiments amplifier 210 is implemented with other than anoperational amplifier. Amplifier 210 is an example of a voltagecontrolled current source capable of increasing the various biascurrents in input transistor 110. Amplifier 210 provides a voltage pathfrom the output of the amplifier 210 to node 111, and also provides acurrent path from node 111 to the output of amplifier 210. Amplifier 210includes an output stage capable of sinking excess bias current comingfrom the emitter of input transistor 110.

FIG. 3 shows a diagram of a circuit including a Darlington transistorpair in accordance with various embodiments of the present invention.Circuit 300 includes elements similar to those shown in circuit 200(FIG. 2), with the addition of cascode transistor 310. Cascodetransistor 310 is coupled between upper power supply node 113 and thecollectors of transistors 110 and 120. In some embodiments, RF choke 112is coupled between cascode transistor 130 and upper power supply node113.

Although cascode transistor 310 is shown in FIG. 3 as a bipolar junctiontransistor, this is not a limitation of the present invention. Forexample, in some embodiments, cascode transistor 310 is an isolated gatefield effect transistor (IGFET), such as a metal oxide semiconductorfield effect transistor (MOSFET). As shown in FIG. 3, a bias voltageVBIAS3 is applied to a control terminal 312 of cascode transistor 310.In embodiments that include a BJT cascode transistor 310, controlterminal 312 may be referred to as a base terminal, and in embodimentsthat include an IGFET transistor 310, control terminal 312 may bereferred to as a gate terminal.

The addition of cascode transistor 310 to circuit 300 may broaden theoperating bandwidth of circuit 300. Further, by modifying the biasvoltage VBIAS3 on control terminal 312, the gain of circuit 300 may bemodified. In some embodiments, VBIAS3 is modified in response to outputsignal characteristics detected on output node 142 to implementautomatic gain control (AGC). Various embodiments including AGC aredescribed below with reference to later figures.

FIG. 4 shows a block diagram of an electronic system. System 400includes antenna 442, amplifier 440, RF processing block 450, digitalprocessing block 460, processor 410, memory 420, and controllable biascircuit 430. Antenna 442 may be either a directional antenna or anomni-directional antenna. For example, in some embodiments, antenna 442may be an omni-directional antenna such as a dipole antenna, or aquarter-wave antenna. Also for example, in some embodiments, antenna 442may be a directional antenna such as a parabolic dish antenna or a Yagiantenna.

Amplifier 440 may be an amplifier that includes a Darlington pair withan increased bias current in an input transistor. For example, amplifier440 may include any of the embodiments represented by circuit 100 (FIG.1), circuit 200 (FIG. 2), or circuit 300 (FIG. 3).

In some embodiments, signals transmitted or received by antenna 442 maycorrespond to voice signals, data signals, or any combination thereof.For example, either or both of RF processing block 450 and digitalprocessing block 460 may include the appropriate circuitry to implementa wireless local area network interface, cellular phone interface,global positioning system (GPS) interface, or the like.

Radio frequency (RF) processing block 450 receives RF signals fromantenna 442 and in various embodiments, performs varying amounts andtypes of signal processing. For example, in some embodiments, RFprocessing block 450 may include oscillators, mixers, filters,demodulators, detectors, decoders, or the like. Also for example, RFprocessing block 450 may perform signal processing such as frequencyconversion, carrier recovery, symbol demodulation, or any other suitablesignal processing.

In some embodiments, RF processing block 450 is controlled by, andprovides information to, processor 410. For example, in someembodiments, the type of demodulation may be influenced by commands orcontrol signals provided to RF processing block 450 by processor 410.Further, in some embodiments, RF processing block 450 may provideinformation such as signal strength or frequency to processor 410.Processor 410 may influence the operation of other blocks shown in FIG.4 in response to information received from RF processing block 450. Forexample, an automatic gain control (AGC) loop may be formed by RFprocessing block 450, processor 410, controllable bias circuit 430, andamplifier 440.

Digital processing block 460 receives a signal from RF processing block450, and performs various amounts and types of digital processing. Forexample, digital processing block 460 may perform de-interleaving,decoding, error recovery, or the like. As described above, digitalprocessing block 460 may include the appropriate circuitry to implementany type of communications system, including but not limited to,wireless networking, cellular telephony, and satellite signal reception.The various embodiments of the present invention are not limited by themany possible physical implementations of digital processing block 460.

The various blocks shown in FIG. 4 are coupled by bus 412. Bus 412 maybe any type of bus including any number of conductors. For example, bus412 may be any type of communications interface, including but notlimited to, a serial interface, a parallel interface, a processor bus, asystem bus, or the like.

In some embodiments, processor 410 may be any suitable processor toinfluence the operation of other circuits such as controllable biascircuit 430. In some embodiments, processor 410 may perform operationsin support of method embodiments of the present invention. For example,processor 410 may perform actions listed in method 600 (FIG. 6),described below. Processor 410 represents any type of processor,including but not limited to, a microprocessor, a microcontroller, adigital signal processor, a personal computer, a workstation, or thelike. Further, processor 410 may be formed of dedicated hardware, suchas state machines or the like.

Memory 420 represents an article that includes a machine readablemedium. For example, memory 420 represents any one or more of thefollowing: a hard disk, a floppy disk, random access memory (RAM),dynamic random access memory (DRAM), static random access memory (SRAM),read only memory (ROM), flash memory, CDROM, or any other type ofarticle that includes a medium readable by a machine such as processor410. In some embodiments, memory 420 can store instructions forperforming the execution of the various method embodiments of thepresent invention.

In operation of some embodiments, processor 410 reads instructions anddata from memory 420 and performs actions in response thereto. Forexample, various method embodiments of the present invention may beperformed by processor 410 while reading instructions from memory 420.

Controllable bias circuit 430 may produce one or more bias voltages andprovide them to amplifier 440. For example, controllable bias circuit430 may produce one or more of VBIAS1, VBIAS2, or VBIAS3 to bias varioustransistors as shown in FIGS. 1-3. In some embodiments, controllablebias circuit 430 includes a voltage controlled current source such asvoltage controlled current source 130 (FIG. 1). In some embodiments,controllable bias circuit 310 includes multiple separately controllablebias circuits to modify the various bias voltages.

Various bias voltages are provided to amplifier 440 on node 432. In someembodiments, node 432 includes multiple physical conductors, eachcarrying a separate bias voltage. In other embodiments, various biasvoltages are multiplexed onto a single conductor of node 432. The numberand type of physical conductors represented by node 432 is not alimitation of the present invention.

As shown in FIG. 4, the various blocks of system 400 may be implementedseparately. In some embodiments, two or more of the blocks shown areimplemented on a single integrated circuit die. For example, processor410 and memory 420 may be implemented on the same integrated circuitalong with digital processing block 460. Also for example, in someembodiments, all of the blocks except for antenna 442 are included on asingle integrated circuit. Any combination of circuits on a singleintegrated circuit die is possible without departing from the scope ofthe present invention.

Although FIG. 4 shows an amplifier used in conjunction with an antenna,this is not a limitation of the present invention. For example, manyelectronic systems may employ amplifier 440 without the use of anantenna. For example, in some embodiments, amplifier 440 is included inan optoelectronic system, and employed to amplify electrical signalsconverted from optical signals. These embodiments do not necessarilyutilize an antenna.

FIG. 5 shows an electronic system in accordance with various embodimentsof the present invention. System 500 includes antenna 442, amplifier440, RF processing block 450, digital processing block 460, processor410, and memory 420. System 500 also includes signal generator 510,digital-to-analog converter (DAC) 520, and analog-to-digital converter(ADC) 530.

Digital-to-analog converter 520 may produce bias voltages and providethem to amplifier 440 on node 522. In some embodiments, DAC 520 servesas one or more controllable bias circuits, such as controllable biascircuit 430 (FIG. 4). Further, in some embodiments, DAC 520 includesmultiple digital-to-analog converters.

Various bias voltages are provided to amplifier 440 on node 522. In someembodiments, node 522 includes multiple physical conductors, eachcarrying a separate bias voltage. In other embodiments, various biasvoltages are multiplexed onto a single conductor of node 522. The numberand type of physical conductors represented by node 522 is not alimitation of the present invention.

In some embodiments, signal generator 510 conditionally drives areference signal at the input of amplifier 440. Also in someembodiments, ADC 530 may measure signal characteristics of signal outputfrom amplifier 440, and provide the signal characteristic information toother blocks in system 500 via bus 512.

System 500 may utilize signal generator 510 to calibrate variousportions of the system, including amplifier 440. For example, processor410 may inject a reference signal into amplifier 440 using signalgenerator 510, measure signal characteristics using ADC 530, and alterbias voltages by influencing the operation of DAC 520. In theseembodiments, bias voltages on an input transistor of a Darlington pairmay be modified to change operating frequency characteristics of, or toreduce noise in, amplifier 440. Also in these embodiments, a biasvoltage on a cascode transistor may be modified to change the gain ofamplifier 440.

An automatic gain control (AGC) control loop may be formed fromamplifier 440, ADC 530, and DAC 520. For example, ADC 530 may measure anoutput signal level, and adjust the output of DAC 520 to influence thegain of amplifier 440.

ADC 530 represents a device capable of measuring signal characteristicsof the output signal driven by amplifier 440. In some embodiments,signal characteristics are measured using a device other than ananalog-to-digital converter. For example, in some embodiments, a peakdetector, an envelope detector, or other signal characteristicmeasurement device is utilized in place of, or in addition to, ADC 530.

The various blocks shown in FIG. 5 are coupled by bus 512. Bus 512 maybe any type of bus including any number of conductors. For example, bus512 may be any type of communications interface, including but notlimited to, a serial interface, a parallel interface, a processor bus, asystem bus, or the like.

As shown in FIG. 5, the various blocks of system 500 may be implementedseparately. In some embodiments, two or more of the blocks shown areimplemented on a single integrated circuit die. For example, processor410 and memory 420 may be implemented on the same integrated circuitalong with digital processing block 460. Also for example, in someembodiments, all of the blocks except for antenna 442 are included on asingle integrated circuit. Any combination of circuits on a singleintegrated circuit die is possible without departing from the scope ofthe present invention.

Although FIG. 5 shows an amplifier used in conjunction with an antenna,this is not a limitation of the present invention. For example, manyelectronic systems may employ amplifier 440 without the use of anantenna. For example, in some embodiments, amplifier 440 is included inan optoelectronic system, and employed to amplify electrical signalsconverted from optical signals. These embodiments to not necessarilyutilize an antenna.

Systems, amplifiers, Darlington transistor pairs, controllable biascircuits, and other embodiments of the present invention can beimplemented in many ways. In some embodiments, they are implemented inintegrated circuits. In some embodiments, design descriptions of thevarious embodiments of the present invention are included in librariesthat enable designers to include them in custom or semi-custom designs.For example, any of the disclosed embodiments can be implemented in asynthesizable hardware design language, such as VHDL or Verilog, anddistributed to designers for inclusion in standard cell designs, gatearrays, or the like. Likewise, any embodiment of the present inventioncan also be represented as a hard macro targeted to a specificmanufacturing process. For example, any of the amplifier embodimentsdescribed herein may be represented as polygons assigned to layers of anintegrated circuit.

FIG. 6 shows a flowchart in accordance with various embodiments of thepresent invention. In some embodiments, method 600, or portions thereof,is performed by an electronic system, a processor, or a control loop,embodiments of which are shown in the various figures. In otherembodiments, all or a portion of method 600 is performed by a controlcircuit or processor. Method 600 is not limited by the particular typeof apparatus or software element performing the method. The variousactions in method 600 may be performed in the order presented, or may beperformed in a different order. Further, in some embodiments, someactions listed in FIG. 6 are omitted from method 600.

Method 600 is shown beginning with block 610 where a bias current in aninput transistor of a Darlington pair is increased. In some embodiments,this corresponds to increasing a collector-to-emitter bias current intransistor 110 (FIGS. 1, 2, 3). In other embodiments, this correspondsto increasing a base-to-emitter bias current in the same transistor. Instill further embodiments, this corresponds to increasing both thecollector-to-emitter bias current and the base-to-emitter bias currentin transistor 110.

At 620, a reference signal is applied to a base of the input transistor.This may correspond to a signal generator such as signal generator 510(FIG. 5) driving a signal on the input of amplifier 440 (FIG. 5). At630, an output voltage of the Darlington pair is measured. The outputvoltage of the Darlington pair may be measured in many different ways.In some embodiments, the output voltage is measured using ananalog-to-digital converter such as ADC 530 (FIG. 5).

At 640, a bias voltage applied to the base of the input transistor ismodified, and at 650, a bias voltage applied to the emitter of the inputtransistor is modified. These bias voltage modifications may serve manydifferent purposes. For example, bias voltage modifications may alterthe magnitude of bias currents in the input transistor of the Darlingtonpair to alter operating characteristics of an amplifier. For example,operating characteristics such as gain-bandwidth product, maximumoperating frequency, and noise figure may be modified by changing thevalues of bias voltages.

At 660, the bias voltage on a cascode transistor coupled between anupper power supply node and the Darlington pair is modified. Forexample, referring now back to FIG. 3, VBIAS3 may be modified toinfluence the operation of cascode transistor 310.

In some embodiments, the various bias voltages referred to above may bemodified in response to signal characteristics of an output signalmeasured at 630. Further, the various bias voltages may be modified inresponse to a relationship between the applied reference signal, andmeasured output voltage characteristics.

Although the present invention has been described in conjunction withcertain embodiments, it is to be understood that modifications andvariations may be resorted to without departing from the spirit andscope of the invention as those skilled in the art readily understand.Such modifications and variations are considered to be within the scopeof the invention and the appended claims.

1. An apparatus comprising: an input transistor and a second transistorcoupled as a Darlington pair; and a bias circuit to increase acollector-to-emitter bias current in the first transistor.
 2. Theapparatus of claim 1 wherein the bias circuit comprises a voltagecontrolled current source.
 3. The apparatus of claim 1 wherein the biascircuit comprises an operational amplifier coupled to maintain asubstantially constant base voltage on the second transistor.
 4. Theapparatus of claim 1 further comprising a cascode transistor coupledbetween an upper power supply node and collectors of the input andsecond transistors.
 5. The apparatus of claim 4 further comprising asecond bias circuit to bias the cascode transistor.
 6. The apparatus ofclaim 1 further comprising a third bias circuit to apply a bias voltageto a base of the input transistor.
 7. The apparatus of claim 6 whereinthe input transistor comprises a heterojunction bipolar transistor. 8.The apparatus of claim 6 wherein the input transistor comprises anIndium Phospate transistor.
 9. The apparatus of claim 1 wherein the biascircuit comprises a digital-to-analog converter.
 10. The apparatus ofclaim 1 further comprising an inductor coupled to a collector of thesecond transistor.
 11. The apparatus of claim 1 further comprising aninductor coupled to an emitter of the second transistor.
 12. Anapparatus comprising: an amplifier including an input transistor and asecond transistor coupled as a Darlington pair; a controllable biascircuit coupled to an emitter of the input transistor; and a controlcircuit to influence operation of the controllable bias circuit.
 13. Theapparatus of claim 12 further comprising a second controllable biascircuit coupled to a base of the input transistor.
 14. The apparatus ofclaim 12 wherein the controllable bias circuit comprises an operationalamplifier coupled as an error amplifier.
 15. The apparatus of claim 14further comprising a low pass filter between an output of theoperational amplifier and the emitter of the input transistor.
 16. Theapparatus of claim 12 wherein the control circuit includes adigital-to-analog converter.
 17. The apparatus of claim 12 wherein thecontrol circuit includes a processor.
 18. The apparatus of claim 12further comprising a cascode transistor coupled between an upper powersupply node and a collector of the input transistor.
 19. The apparatusof claim 18 further comprising a controllable bias circuit coupled to acontrol node of the cascode transistor.
 20. The apparatus of claim 19wherein the control circuit is coupled to influence operation of thecontrollable bias circuit for the cascode transistor.
 21. The apparatusof claim 19 further comprising an automatic gain control circuit coupledbetween an output of the amplifier and the controllable bias circuit forthe cascode transistor.
 22. An electronic system comprising: an antenna;an amplifier coupled to the antenna, the amplifier including an inputtransistor and a second transistor coupled as a Darlington pair; acontrollable bias circuit coupled to an emitter of the input transistor;and a control circuit to influence operation of the controllable biascircuit.
 23. The electronic system of claim 22 further comprising asecond controllable bias circuit coupled to a base of the inputtransistor.
 24. The electronic system of claim 22 wherein thecontrollable bias circuit comprises an operational amplifier coupled asan error amplifier.
 25. The electronic system of claim 22 wherein thecontrol circuit comprises a processor.
 26. A method comprisingincreasing a bias current in an input transistor of a Darlington pair byproviding a current path from, and a voltage path to, an emitter of theinput transistor.
 27. The method of claim 26 further comprising:applying a reference signal to a base of the input transistor; andmeasuring an output voltage of the Darlington pair.
 28. The method ofclaim 27 further comprising modifying a bias voltage applied to the baseof the input transistor.
 29. The method of claim 27 wherein increasing abias current comprises changing a bias voltage on a voltage controlledcurrent source.
 30. The method of claim 27 further comprising modifyinga bias voltage on a cascode transistor coupled between an upper powersupply node and the Darlington pair.